Op-Amp

The operational amplifier is the workhorse building block of analog design, and understanding its internal topology is essential for anything from simple buffers to high-resolution data converters. The two-stage Miller-compensated op-amp remains a canonical teaching topology: a differential pair input stage provides high gain and sets common-mode rejection, while a second common-source gain stage boosts output swing, with a Miller capacitor (often with a nulling resistor) providing frequency compensation for stability in feedback. Single-stage telescopic and folded-cascode amplifiers trade output swing for higher bandwidth and simpler compensation, and are common in switched-capacitor applications where output swing requirements are relaxed.

Key specifications include open-loop gain (DC gain, often 60-100dB), gain-bandwidth product, slew rate (limited by the bias current charging the compensation capacitor), input offset voltage (driven by device mismatch), CMRR and PSRR (common-mode and power-supply rejection), and output swing (rail-to-rail designs use complementary input pairs and class-AB output stages to maximize headroom). The choice between single-ended and fully differential topologies affects common-mode feedback (CMFB) requirements — fully differential amplifiers need an explicit CMFB loop to set the output common-mode level, since differential feedback alone does not constrain it.

Advanced techniques include rail-to-rail input/output stages, class-AB output stages for driving low-impedance loads efficiently, gain-boosting (regulated cascode) to push DC gain beyond what cascoding alone provides, and chopper/auto-zero techniques to cancel offset and 1/f noise in precision instrumentation amplifiers. Op-amp design is fundamentally an exercise in balancing gain, bandwidth, noise, power, swing, and stability — and nearly every other analog block (bandgaps, LDOs, ADCs/DACs, filters) is built around one or more amplifier cores.

Resume Tips

Join VLSI Korea

Follow vlsi.kr for semiconductor design career guides, tooling deep-dives, and updates to these roadmaps.

Roadmaps STA Physical Design RTL Design Design Verification vlsi.kr Blog

VLSI Korea Roadmaps

Interactive career roadmaps for semiconductor design — Static Timing Analysis, Physical Design, RTL Design, Verification, Analog Design, DFT, and EDA Toolflow Engineering. Built for students, junior engineers, and experienced professionals.

© VLSI Korea · vlsi.kr