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Analog / Mixed-Signal Design
Design op-amps, bandgaps, PLLs, data converters. From small-signal analysis to layout parasitics.
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Open any concept as a complete, shareable learning page with its own URL and related-topic navigation.- ADC/DAC Data converters bridge the analog and digital domains, and architecture selection depends heavily on the target resolution, speed, and power budget. The successive approximation register (SAR) ADC has become dominant for medium-resolution (8-14 bit), medium-speed applications due to its excellent energy efficiency — it uses a binary search algorithm, a comparator, and a capacitive DAC (CDAC) to converge on the input voltage one bit at a time. Pipeline ADCs use multiple stages of coarse flash conversion plus residue amplification (via multiplying DACs and residue amplifiers) to achieve high resolution at high speed, while sigma-delta (ΔΣ) converters oversample and use noise-shaping (via a modulator loop) combined with digital decimation filters to push quantization noise out of band, achieving very high resolution for audio, sensor, and precision measurement applications at the cost of bandwidth.
- Bandgap The bandgap voltage reference generates a stable voltage (typically ~1.2V) that is largely independent of temperature and supply variation, serving as the foundation for biasing, ADC references, and LDO regulation across the chip. The core principle is combining two voltages with opposite temperature coefficients: the base-emitter voltage VBE of a bipolar transistor (or diode), which decreases with temperature (CTAT, complementary-to-absolute-temperature), and the difference in VBE between two BJTs operating at different current densities, ΔVBE, which increases with temperature (PTAT, proportional-to-absolute-temperature). Summing VBE with a scaled ΔVBE (multiplied by a resistor ratio) cancels the first-order temperature dependence, yielding the bandgap voltage of roughly 1.2V.
- Comparator A comparator determines which of two input voltages is larger, producing a digital output, and is a critical block in ADCs, oscillators, switching regulators, and level detectors. Unlike an op-amp used in a closed feedback loop, a comparator is typically used open-loop and is optimized for speed and decision accuracy rather than linearity. Topologies range from simple differential pairs followed by gain/inverter stages, to dynamic latch-based comparators (StrongARM latch) that use positive feedback (cross-coupled inverters) to regenerate a small input difference into a full-swing digital output extremely quickly, with regeneration time constant set by gm/C of the latch.
- EM/IR Electromigration (EM) and IR drop analysis verify that the power, ground, and signal routing in an analog layout can reliably carry the required currents without degrading performance or causing long-term reliability failures. EM occurs when high current density in a metal interconnect causes metal atoms to migrate via momentum transfer with electrons, gradually thinning the conductor at one end and accumulating material (creating voids and hillocks) until the wire opens or shorts to a neighbor — failure rates increase exponentially with current density and temperature (described by Black's equation), so each metal layer and via has a maximum allowed current density (often specified separately for DC and average/RMS AC currents).
- ESD Electrostatic discharge (ESD) protection circuits shield IC pads and internal circuitry from high-voltage, high-current transient events (human body model, machine model, charged device model) that can occur during handling and assembly. ESD design requires creating a low-impedance discharge path that triggers fast enough and clamps voltage low enough to prevent gate oxide rupture or junction damage in the protected core circuit, while remaining transparent (high impedance, low capacitance) during normal operation.
- Extraction Parasitic extraction (PEX) generates a netlist of resistances and capacitances (and, for high-frequency designs, inductances) introduced by the actual layout geometry — interconnect, vias, and device-level routing — that are absent from the pre-layout schematic. For analog circuits, these parasitics are not second-order effects to be ignored; a few femtofarads of extra capacitance on a high-impedance node in an op-amp can shift a pole enough to degrade phase margin, and resistance in a current mirror's source connection can introduce systematic offset.
- Freq Response Frequency response analysis determines how an analog circuit's gain and phase behave across frequency, which directly governs stability, bandwidth, and settling time. Every node in a circuit has an associated resistance and capacitance that form a pole; the dominant pole (lowest frequency pole) typically sets the -3dB bandwidth, while higher-frequency poles and zeros determine phase margin and stability when the circuit is placed in feedback. The Miller effect — where a capacitor between the input and output of an inverting gain stage is multiplied by (1+Av) when reflected to the input — is one of the most important mechanisms shaping frequency response in op-amps and is exploited deliberately for compensation.
- LDO A low-dropout regulator (LDO) provides a clean, regulated voltage from a noisier or higher supply, using a pass transistor (in linear, not switching, operation) controlled by a feedback amplifier that compares a divided-down output voltage against a reference. Because the pass device operates as a variable resistor rather than switching, LDOs are inherently low-noise and fast-responding compared to switching regulators, making them ideal for powering noise-sensitive analog blocks like PLLs, VCOs, and precision references, at the cost of efficiency (proportional to VOUT/VIN, since the dropout voltage is dissipated as heat).
- Matching Device matching is the layout discipline of ensuring that nominally identical transistors, resistors, and capacitors behave as identically as possible despite random and systematic variation across the die. Random mismatch follows Pelgrom's law, where the variance of a parameter mismatch (e.g., threshold voltage ΔVT) is inversely proportional to device area (WL) — larger devices match better but cost area and add capacitance, so matching-critical devices (differential pair inputs, current mirror legs, bandgap BJTs) are sized as a direct trade-off against bandwidth and power.
- Mirrors Current mirrors are the basic building block for biasing nearly every analog circuit, copying a reference current to one or more branches with a ratio set by transistor sizing (W/L ratios). The simple two-transistor mirror relies on both devices having the same VGS and operating in saturation; accuracy depends on matching threshold voltage, mobility, and channel length between the reference and output devices, which is why mirror transistors are typically laid out with identical orientation, common-centroid arrangements, and sufficient length to minimize the impact of random mismatch (governed by Pelgrom's law, where mismatch variance scales as 1/(WL)).
- Noise Noise analysis quantifies the random fluctuations that fundamentally limit the resolution and dynamic range of analog circuits. The two dominant noise sources in MOSFETs are thermal noise, generated by the channel resistance (modeled as a current source with PSD = 4kT·gamma·gm), and flicker (1/f) noise, caused by traps at the Si-SiO2 interface that capture and release carriers, with a power spectral density proportional to 1/f and inversely proportional to device area (WL). Flicker noise dominates at low frequencies and is a key reason analog designers use large gate areas for input devices in precision amplifiers and why techniques like chopping and correlated double sampling exist.
- Op-Amp The operational amplifier is the workhorse building block of analog design, and understanding its internal topology is essential for anything from simple buffers to high-resolution data converters. The two-stage Miller-compensated op-amp remains a canonical teaching topology: a differential pair input stage provides high gain and sets common-mode rejection, while a second common-source gain stage boosts output swing, with a Miller capacitor (often with a nulling resistor) providing frequency compensation for stability in feedback. Single-stage telescopic and folded-cascode amplifiers trade output swing for higher bandwidth and simpler compensation, and are common in switched-capacitor applications where output swing requirements are relaxed.
- Physics Analog design begins with the physics of the MOSFET. Beyond the simple square-law I-V relationship, practical analog circuits operate across all regions of operation — subthreshold, triode, and saturation — and the choice of region directly determines the trade-off between gain, speed, noise, and power. In modern CMOS nodes, short-channel effects such as velocity saturation, drain-induced barrier lowering (DIBL), and channel-length modulation cause the drain current to deviate significantly from the long-channel model, making gm/ID-based design methodologies more reliable than closed-form equations for sizing transistors.
- PLL/DLL A phase-locked loop (PLL) generates a clock whose phase and frequency are locked to a reference, and is central to clock generation, frequency synthesis, and clock-data recovery. The core building blocks are a phase/frequency detector (PFD) that compares the reference and feedback clock phases, a charge pump that converts the PFD output into a current driving a loop filter, a loop filter that integrates this into a control voltage, a voltage-controlled oscillator (VCO) that produces the output frequency proportional to that control voltage, and a feedback divider that scales the VCO frequency down to compare against the reference. The loop dynamics are characterized by loop bandwidth and phase margin, analogous to any feedback system, and determine lock time, jitter transfer, and reference spur suppression.
- Post-Sim Post-layout simulation re-runs the same simulation suite used for schematic-level verification (DC operating point, AC/stability, transient, noise, Monte Carlo) but with the parasitic-extracted netlist, revealing how layout-induced resistance and capacitance shift performance specs from their pre-layout values. A common workflow is to compare key metrics — gain, bandwidth, phase margin, offset, noise, settling time, PSRR — pre- and post-layout, and to flag any spec that degrades beyond an acceptable margin or violates the target altogether, since the schematic-level design typically must leave headroom for exactly this degradation.
- Small-Signal Small-signal analysis is the foundational technique for analyzing analog circuits around a DC operating point. After establishing the bias point (the large-signal solution), each nonlinear device is replaced by a linear small-signal model — a MOSFET becomes a transconductance gm, an output resistance ro, and parasitic capacitances. This linearization allows the use of superposition, KCL/KVL, and standard two-port theory to compute gain, input/output impedance, and frequency response without solving the full nonlinear equations.
