Compression

Test compression addresses the mismatch between the number of internal scan chains a design can support (often thousands, for short chains and fast test time) and the limited number of pins/channels available on the tester (typically tens). On-chip decompressor and compactor logic sits between the tester channels and the internal scan chains: the decompressor (often implemented as an XOR/XNOR fan-out network or a ring of programmable broadcast logic) expands a small number of tester input channels into many internal scan chain inputs, while the compactor (typically an XOR tree or a more sophisticated selective compactor) compresses many chain outputs down to a small number of tester output channels.

The dominant commercial architectures are embedded deterministic test (EDT, Synopsys/Siemens heritage) and similar ring-based or combinational compression schemes from other vendors, generally offering compression ratios from roughly 10x to over 100x depending on the number of internal chains versus external channels. Because multiple internal chains share a compactor XOR tree, an unknown (X) value captured in any one chain can corrupt the observed value for all chains sharing that XOR cone; X-bounding and dedicated X-masking logic (sometimes integrated into the compactor itself) are essential to prevent unpredictable values from invalidating large portions of a pattern.

Compression dramatically reduces ATE test time and pattern memory requirements, which is the primary economic justification for the area overhead of the decompressor/compactor logic, typically a few percent of die area. Design considerations include selecting the compression ratio based on expected pattern counts and available test pins, ensuring the decompressor's combinational logic doesn't create excessive routing congestion near the scan chain endpoints, and verifying that the compression network itself is testable (often via a bypass mode that allows direct, uncompressed access to chains for diagnosis). During failure diagnosis, compacted responses must be "unrolled" or the design switched to a bypass/serial mode to localize the failing scan cell precisely.

Resume Tips

Join VLSI Korea

Follow vlsi.kr for semiconductor design career guides, tooling deep-dives, and updates to these roadmaps.

Visit vlsi.kr Articles, tools, and career resources

Roadmaps STA Physical Design RTL Design Design Verification vlsi.kr Blog

VLSI Korea Roadmaps

Interactive career roadmaps for semiconductor design — Static Timing Analysis, Physical Design, RTL Design, Verification, Analog Design, DFT, and EDA Toolflow Engineering. Built for students, junior engineers, and experienced professionals.

© VLSI Korea · vlsi.kr