Defects

A defect is a physical imperfection in a manufactured die, while a fault is the logical model used to represent that defect's electrical effect for test purposes; understanding the mapping between the two is essential for building effective DFT strategies. Common defect mechanisms include particle contamination causing shorts or opens, photolithography variations leading to thinning or bridging of metal lines, via voids, gate oxide breakdown, and process-induced threshold voltage shifts. Random defects scale roughly with die area and tend to dominate yield loss for mature processes, while systematic defects relate to specific layout patterns or process steps and require design-for-manufacturability (DFM) analysis to address.

Defects manifest electrically in several characteristic ways. A short (bridging defect) connects two nodes that should be electrically isolated, producing wired-AND or wired-OR behavior depending on the driving strengths, and can also create resistive bridges that cause delay degradation rather than a hard logic error. An open defect breaks a connection, which in CMOS can leave a node in a high-impedance state that retains its previous value (a stuck-open fault), making it sequentially dependent and harder to detect with single-pattern tests. Resistive opens and shorts are particularly troublesome because they may pass functional test at nominal conditions but fail under voltage, temperature, or frequency variation, contributing to field returns and "no trouble found" failures.

Because no single fault model captures every defect type, modern test programs use a layered approach: stuck-at patterns catch many hard shorts and opens, transition/delay patterns catch resistive and timing-related defects, and cell-aware or bridging fault models target defects specific to the transistor-level implementation of standard cells. Defect-based test methodologies use inline silicon failure analysis (layout extraction of likely defect locations) to generate fault lists that better reflect actual process defect distributions, improving the correlation between simulated fault coverage and real-world DPPM.

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