Transition

Transition fault testing, also called at-speed test or AC scan, targets timing-related defects that stuck-at patterns cannot catch because stuck-at ATPG runs at slow speed and only checks final logic values, not how quickly a signal arrives. The transition fault model assumes each gate output can exhibit either a slow-to-rise (stuck-at-0-like delay) or slow-to-fast (stuck-at-1-like delay) fault, and detecting it requires a two-pattern sequence: an initialization vector that sets the target node to the opposite value, followed by a launch pattern applied at functional clock speed and a capture that samples the response after exactly one clock period (or a small multiple of it).

Two clocking schemes are used to apply the launch-capture pair at speed. Launch-on-shift (LOS), also called skewed-load, uses the last shift clock pulse as the launch event, so the launch and capture clock edges are separated by exactly one functional period, giving maximum at-speed coverage but requiring the scan enable signal itself to switch at speed, which can be difficult for some scan architectures. Launch-on-capture (LOC), or broadside, uses two capture clock pulses with scan_enable held low between them, avoiding the at-speed scan enable requirement but generating launch states that come only from previously captured (functional-like) values, which can slightly reduce achievable coverage. Most designs support LOC, with LOS used selectively where the clocking architecture allows it.

At-speed transition test requires careful clock domain handling: each clock domain under test needs its own at-speed launch/capture pulse generated by on-chip test clock controllers (often built from the PLL or a dedicated clock-control macro), since the tester itself typically cannot supply the GHz-range edges needed. Multi-cycle and clock-domain-crossing paths require special "skip" or "extra clock" handling so capture happens at the correct cycle. Transition pattern sets are usually generated after timing-aware netlist information (post-layout SDF or estimated wire delays) is available, since the goal is to exercise the actual critical paths of the design, and coverage is reported separately from stuck-at coverage as part of the overall test quality signoff.

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