Formal

Formal verification uses mathematical proof techniques — rather than simulation with test vectors — to verify properties of a design exhaustively across all possible input sequences and states. Where simulation can only show that a design behaves correctly for the specific stimulus exercised, formal tools (e.g., Synopsys VC Formal, Cadence JasperGold) can prove that a property holds for every possible input, or find a concrete counterexample (a "waveform") demonstrating a violation.

The most common entry point for RTL designers is property checking using SystemVerilog Assertions: an assert property written for simulation can often be handed directly to a formal tool, which attempts to prove the property holds for all reachable states, or returns a counterexample trace if it doesn't. This is especially powerful for control logic — FSMs, arbiters, interface protocol compliance — where the state space is large enough that simulation is unlikely to hit every corner case, but small enough that formal tools can exhaustively explore it (the state space explosion problem limits formal's applicability to very large datapaths, which is why formal tends to focus on control-dominant blocks).

Specific formal applications relevant to RTL design include: reachability/dead-code analysis (proving certain states or branches can never be reached, often revealing RTL bugs or redundant logic — complementary to simulation coverage), X-propagation checking (proving that an uninitialized or unknown value cannot influence a critical output), connectivity checking (verifying that thousands of SoC-level signal connections match a specification, infeasible to check manually or via simulation), and CDC formal analysis (statically verifying synchronizer structures are correctly implemented at every clock domain crossing).

Equivalence checking (LEC) is a related but distinct formal technique: rather than checking a property, it proves that two representations of a design (RTL vs. gate-level netlist, or pre- vs. post-ECO netlist) are functionally equivalent — the standard sign-off step after synthesis and after any manual netlist edits, replacing exhaustive gate-level simulation for that purpose.

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