JTAG 1149.1
IEEE 1149.1, commonly called JTAG (Joint Test Action Group) or boundary scan, defines a standard four- or five-wire serial interface (TCK clock, TMS mode select, TDI/TDO serial data, and optional TRST reset) and an on-chip Test Access Port (TAP) controller for accessing test and debug logic without dedicated pins per function. The TAP controller is a 16-state finite state machine driven by TCK and TMS that moves between states for selecting instruction or data registers, shifting data in and out, and updating register contents, providing a uniform protocol regardless of the specific test logic behind it.
Two mandatory registers anchor the standard: the instruction register (IR), which selects which data register is active and what operation is performed (e.g., BYPASS, EXTEST, SAMPLE/PRELOAD, IDCODE), and the boundary scan register, a chain of boundary scan cells placed at each I/O pin that can capture the pin's value (SAMPLE), drive a value onto the pin while isolating it from the core logic (EXTEST, useful for board-level interconnect test), or shift values without affecting pins (PRELOAD). The BYPASS register provides a single-bit shortcut through a device when its boundary scan register isn't the target, important for multi-device JTAG chains where several ICs share the same TCK/TMS/TDI/TDO bus.
In modern SoCs, JTAG's role extends well beyond its original board-level interconnect test purpose: it serves as the universal access point for on-chip debug (connecting to ARM CoreSight, RISC-V debug modules, or similar), for triggering and reading back results from MBIST and LBIST controllers, for accessing fuse/eFuse programming logic, and for boundary-scan-described-in-hardware (BSDL) files that EDA and board-test tools use to generate interconnect tests automatically. Because of its central role in debug and manufacturing, JTAG access is also a security concern, and many designs implement IEEE 1149.1-compliant access control or authentication mechanisms (related to IEEE 1149.7 and proprietary lock/unlock schemes) to restrict TAP access in production devices.
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[Book] IEEE Std 1149.1 Boundary-Scan Test Standard(https://www.amazon.com/s?k=IEEE+1149.1+boundary+scan+test+standard+JTAG)
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[Coursera] JTAG boundary scan IEEE 1149.1(https://www.udemy.com/courses/search/?q=JTAG+boundary+scan+IEEE+1149.1)
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[YouTube] JTAG TAP controller boundary scan tutorial(https://www.youtube.com/results?search_query=JTAG+TAP+controller+boundary+scan+tutorial)